CHAPTER 3 PROTECTED-MODE MEMORY MANAGEMENT

3.1. MEMORY MANAGEMENT OVERVIEW

The memory management facilities of the IA-32 architecture are divided into two parts: segmentation and paging. Segmentation provides a mechanism of isolating individual code, data, and stack modules so that multiple programs (or tasks) can run on the same processor without interfering with one another. Paging provides a mechanism for implementing a conventional demand-paged, virtual-memory system where sections of a program’s execution environment are mapped into physical memory as needed. Paging can also be used to provide isolation between multiple tasks. When operating in protected mode, some form of segmentation must be used. There is no mode bit to disable segmentation. The use of paging, however, is optional.

IA-32架構(gòu)的內(nèi)存管理機(jī)構(gòu)（facilities）可劃分為兩個(gè)部分：分段（segmentation）和分頁（paging）。分段功能提供了分隔 代碼、數(shù)據(jù)和堆棧的機(jī)制，從而使多個(gè)進(jìn)程運(yùn)行在同一個(gè)CPU物理地址空間內(nèi)而互不影響；分頁可用來實(shí)現(xiàn)一種“請求頁式（demand-paged）”的虛 擬內(nèi)存機(jī)制，從而頁化程序執(zhí)行環(huán)境，在程序運(yùn)行時(shí)可將所需要的頁映射到物理內(nèi)存。分頁機(jī)制也可用作隔離多進(jìn)程任務(wù)。分段功能是CPU保護(hù)模式必須的，沒有 設(shè)置位可以屏蔽內(nèi)存分段；不過內(nèi)存分頁則是可選的。

These two mechanisms (segmentation and paging) can be configured to support simple single-program (or single-task) systems, multitasking systems, or multiple-processor systems that used shared memory.

As shown in Figure 3-1, segmentation provides a mechanism for dividing the processor’s addressable memory space (called the linear address space) into smaller protected address spaces called segments. Segments can be used to hold the code, data, and stack for a program or to hold system data structures (such as a TSS or LDT). If more than one program (or task) is running on a processor, each program can be assigned its own set of segments. The processor then enforces the boundaries between these segments and insures that one program does not interfere with the execution of another program by writing into the other program’s segments.

分段和分頁機(jī)制被配置成支持單任務(wù)系統(tǒng)、多任務(wù)系統(tǒng)或多處理器系統(tǒng)。

如圖3-1，內(nèi)存分段將CPU的可尋址空間（稱為線性地址空間）劃分更小的受保護(hù)的內(nèi)存段，這些段存放程序的數(shù)據(jù)（代碼、數(shù)據(jù)和堆棧）和系統(tǒng)的數(shù)據(jù)結(jié)構(gòu) （像TSS 或 LDT）。如果處理器運(yùn)行著多個(gè)任務(wù)，那么每個(gè)任務(wù)都有一集自己獨(dú)立的內(nèi)存段。

The segmentation mechanism also allows typing of segments so that the operations that may be performed on a particular type of segment can be restricted.

All the segments in a system are contained in the processor’s linear address space. To locate a byte in a particular segment, a logical address (also called a far pointer) must be provided. A logical address consists of a segment selector and an offset. The segment selector is a unique identifier for a segment. Among other things it provides an offset into a descriptor table (such as the global descriptor table, GDT) to a data structure called a segment descriptor. Each segment has a segment descriptor, which specifies the size of the segment, the access rights and privilege level for the segment, the segment type, and the location of the first byte of the segment in the linear address space (called the base address of the segment). The offset part of the logical address is added to the base address for the segment to locate a byte within the segment. The base address plus the offset thus forms a linear address in the processor’s linear address space.

進(jìn)程的各個(gè)段都必須位于CPU的線性空間之內(nèi)，進(jìn)程要訪問某段的一個(gè)字節(jié)，必須給出該字節(jié) 的邏輯地址（也叫遠(yuǎn)指針）。邏輯地址由段選擇子（segment selector ）和偏移值組成。段選擇子是段的唯一標(biāo)識，指向一個(gè)叫段描述符的數(shù)據(jù)結(jié)構(gòu)；段描述符位于一個(gè)叫描述表之內(nèi)（如全局描述表GDT）; 每個(gè)段必須都有相應(yīng)的段描述符，用以指定段大小、訪問權(quán)限和段的特權(quán)級別（privilege level）、段類型和段的首地址在線性地址空間的位置（叫段的基地址）。邏輯地址通過基地址加上段內(nèi)偏移得到。

If paging is not used, the linear address space of the processor is mapped directly into the physical address space of processor. The physical address space is defined as the range of addresses that the processor can generate on its address bus.

Because multitasking computing systems commonly define a linear address space much larger than it is economically feasible to contain all at once in physical memory, some method of “virtualizing” the linear address space is needed. This virtualization of the linear address space is handled through the processor’s paging mechanism.

如果不用分頁功能，處理器的[線性地址空間]就會(huì)直接映射到[物理地址空間]。[物理地址空間]的大小就是處理器能通過地址總線產(chǎn)生的地址范圍。為了直接 使用線性地址空間從而簡化編程和實(shí)現(xiàn)多進(jìn)程而提高內(nèi)存的利用率，需要實(shí)現(xiàn)某種對線性地址空間進(jìn)行“虛擬化（virtualizing）”，CPU的分頁機(jī) 制實(shí)現(xiàn)了這種虛擬化。

Paging supports a “virtual memory” environment where a large linear address space is simulated with a small amount of physical memory (RAM and ROM) and some disk storage. When using paging, each segment is divided into pages (typically 4 KBytes each in size), which are stored either in physical memory or on the disk. The operating system or executive maintains a page directory and a set of page tables to keep track of the pages. When a program (or task) attempts to access an address location in the linear address space, the processor uses the page directory and page tables to translate the linear address into a physical address and then performs the requested operation (read or write) on the memory location. If the page being accessed is not currently in physical memory, the processor interrupts execution of the program (by generating a page-fault exception). The operating system or executive then reads the page into physical memory from the disk and continues executing the program.

“虛擬內(nèi)存”就是利用物理內(nèi)存和磁盤來對CPU的線性地址進(jìn)行模擬（kemin:高級語言源碼指定的是符號地址，是虛的，有了虛擬內(nèi)存即便是用匯編指定一 固定地址也是虛的。問題是這些虛存是怎么管理的）。當(dāng)使用分頁時(shí)，進(jìn)程的每個(gè)段都會(huì)被分成大小固定的頁，這些頁可能在內(nèi)存中，也可能在磁盤。操作系統(tǒng)用了 一張頁目錄（page directory）和多張頁表來管理這些頁。當(dāng)進(jìn)程試圖訪問線性地址空間的某個(gè)位置，處理器會(huì)通過頁目錄和頁表先將線性地址轉(zhuǎn)換成物理地址，然后再訪問 （讀或?qū)懀╧emin：轉(zhuǎn)換細(xì)節(jié)沒有講）。如果被訪問的頁當(dāng)前不在內(nèi)存，處理就會(huì)中斷進(jìn)程的運(yùn)行（通過產(chǎn)生缺頁異常中斷）（kemin:怎么判斷某頁不 在內(nèi)存？）。操作系統(tǒng)負(fù)責(zé)從磁盤讀入該頁并繼續(xù)執(zhí)行該進(jìn)程（kemin:頁讀入的前前后后沒有講）。

When paging is implemented properly in the operating-system or executive, the swapping of pages between physical memory and the disk is transparent to the correct execution of a program. Even programs written for 16-bit IA-32 processors can be paged (transparently) when they are run in virtual-8086 mode.

from:

http://blog.csdn.net/keminlau/archive/2008/10/19/3090337.aspx