if(locked==false) { locked=true; doSomething();}這不是兩個(gè)原子操作？如何防止兩步之間沒(méi)有人插入？
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@shbooom
不是locked，是dosomething.
線程A
if(doSomething==true) { DoSomething(); doSomething=false;}

線程B
if(doSomething==false) { DoOtherthing(); doSomething=true;}

在A線程DoSomething()時(shí)，B線程進(jìn)不去判斷，所以不會(huì)用DoOtherthing()來(lái)干擾。

或者就按照你的locked
修改成這樣
線程A
if(locked==false) { doSomething(); locked=true;}
線程B
if(locked) { doOtherthing(); locked = false;}

在A的花括號(hào)內(nèi)，B的doOtherthing不會(huì)影響A的doSomething。





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Intel Architectures Software Developer's Manual Volume 3A System Programming Guide Chapter 7 Section 2
7.2.2 Memory Ordering in P6 and More Recent Processor Families
The Intel Core 2 Duo, Intel Atom, Intel Core Duo, Pentium 4, and P6 family proces-
sors also use a processor-ordered memory-ordering model that can be further
defined as "write ordered with store-buffer forwarding." This model can be character-
ized as follows.
In a single-processor system for memory regions defined as write-back cacheable,
the following ordering principles apply (Note the memory-ordering principles for
single-processor and multiple-processor systems are written from the perspective of
software executing on the processor, where the term "processor" refers to a logical
processor. For example, a physical processor supporting multiple cores and/or
HyperThreading Technology is treated as a multi-processor systems.):
1 Reads are not reordered with other reads.
2 Writes are not reordered with older reads.
3 Writes to memory are not reordered with other writes, with the exception of
writes executed with the CLFLUSH instruction and streaming stores (writes)
executed with the non-temporal move instructions (MOVNTI, MOVNTQ,
MOVNTDQ, MOVNTPS, and MOVNTPD).
4 Reads may be reordered with older writes to different locations but not with older
writes to the same location.
5 Reads or writes cannot be reordered with I/O instructions, locked instructions, or
serializing instructions.
6 Reads cannot pass LFENCE and MFENCE instructions.
7 Writes cannot pass SFENCE and MFENCE instructions.
In a multiple-processor system, the following ordering principles apply:
1 Individual processors use the same ordering principles as in a single-processor
system.
2 Writes by a single processor are observed in the same order by all processors.
3 Writes from an individual processor are NOT ordered with respect to the writes
from other processors.
4 Memory ordering obeys causality (memory ordering respects transitive
visibility).
5 Writes to the same location have a total order.
6 Locked instructions have a total order.

其實(shí)只有寫(xiě)操作和其后的讀操作(不同的地址)才會(huì)亂序執(zhí)行  回復(fù)  更多評(píng)論
  

看了你之前的源代碼,當(dāng)線程A需要放入數(shù)據(jù)時(shí)B線程一直在使用數(shù)據(jù)的話，線程A會(huì)占100%的CPU，系統(tǒng)里可不光A，B兩個(gè)線程，如果使用系統(tǒng)提供的臨界區(qū)，線程A會(huì)陷入內(nèi)核然后釋放出CPU控制權(quán)，等線程B處理完會(huì)將A喚醒，提高了系統(tǒng)的利用率。  回復(fù)  更多評(píng)論
  

@cpm
代碼中的賦值是在一起的，而且是對(duì)不同的變量，所以他們可能會(huì)被亂序執(zhí)行。這樣另一個(gè)線程獲取到通過(guò)狀態(tài)后，可能這時(shí)候其他的寫(xiě)操作還沒(méi)有執(zhí)行完。就會(huì)出問(wèn)題。

所以在修改狀態(tài)前，要用一個(gè)寫(xiě)barrier來(lái)過(guò)濾掉其他寫(xiě)操作的reorder，從而實(shí)現(xiàn)修改狀態(tài)時(shí)，所有寫(xiě)操作都完成。


另外，關(guān)于例程的代碼，只是做分析用。實(shí)際使用時(shí)，還是得用一些手段來(lái)讓系統(tǒng)對(duì)線程進(jìn)行調(diào)度。這個(gè)是最基本的常識(shí)。
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@飯中淹
3 Writes to memory are not reordered with other writes, with the exception ...
所以寫(xiě)操作和寫(xiě)操作之間不會(huì)亂序（例外情況這里不會(huì)遇到）
同時(shí)
2 Writes by a single processor are observed in the same order by all processors.
因此，一個(gè)線程的寫(xiě)操作也是被所有線程依次觀察到的（例如一個(gè)線程先寫(xiě)了a，后寫(xiě)了b，那么所有線程觀察的結(jié)果都是a先被寫(xiě)，b后被寫(xiě)）
所以這種情況下不需要內(nèi)存屏障，只要變量加了volatile保證編譯器不優(yōu)化就沒(méi)有問(wèn)題


另外，你的代碼之所以無(wú)鎖能夠運(yùn)行，是因?yàn)橥ǔＰ枰嗑€程鎖的那些線程地位是對(duì)等的，而在你的例子里，其實(shí)是把一個(gè)單線程問(wèn)題披上了多線程的外套。A線程只會(huì)把iState 由false改為true，而B(niǎo)線程只會(huì)把iState 由true改為false。既然這樣，為何不讓A線程檢查完直接處理呢？
而真正需要多線程同步的問(wèn)題（即不能簡(jiǎn)化為單線程的問(wèn)題），鎖是不可避免的。就算是lock-free編程，也是使用了硬件鎖。  回復(fù)  更多評(píng)論
  

@cpm
在這里，我說(shuō)的是個(gè)多線程通信問(wèn)題，它的單個(gè)任務(wù)是線性的。
我認(rèn)為：

所有的多線程問(wèn)題都可以細(xì)分為單個(gè)線性任務(wù)。

不能細(xì)分為線性任務(wù)的問(wèn)題，是不存在的。

鎖是不可避免的，就算是狀態(tài)也是一種鎖。

這里的無(wú)鎖，就是不用系統(tǒng)提供的鎖。

無(wú)論是什么多線程問(wèn)題，鎖都是保證線性任務(wù)線性執(zhí)行的。

所以沒(méi)有你說(shuō)的不能簡(jiǎn)化為單線程的問(wèn)題。

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@cpm
另外，我準(zhǔn)備用barrier來(lái)代替volatile，從而讓所有的讀寫(xiě)操作都能夠被優(yōu)化，并且，還能夠獲得及時(shí)的更新。
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為什么不使用Intel的線程開(kāi)發(fā)包TBB呢？這個(gè)庫(kù)已經(jīng)被多個(gè)產(chǎn)品使用了，而不是實(shí)驗(yàn)性代碼。
里面有模板 atomic<T> 來(lái)設(shè)定原子性變量，來(lái)代替volatile, 既保證正確性，又保證跨平臺(tái)。你們擔(dān)心的問(wèn)題，我相信Intel的工程師都已經(jīng)考慮到并且保證沒(méi)有問(wèn)題的。  回復(fù)  更多評(píng)論