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# re: VHDL語(yǔ)言數(shù)字鐘 2007-12-07 21:49 454

1545  回復(fù)  更多評(píng)論   

# re: VHDL語(yǔ)言數(shù)字鐘 2007-12-07 21:49 454

87  回復(fù)  更多評(píng)論   

# re: VHDL語(yǔ)言數(shù)字鐘 2007-12-11 21:11 rgh

xiexie   回復(fù)  更多評(píng)論   

# re: VHDL語(yǔ)言數(shù)字鐘 2007-12-24 00:54 余波

這東西太好了  回復(fù)  更多評(píng)論   

# re: VHDL語(yǔ)言數(shù)字鐘 2007-12-24 01:44 余波

要是能把星期加上就好了
呵呵，這個(gè)嘛，我自己可以完成的喔
不過(guò)有點(diǎn)不明白，你為什么沒(méi)有用防抖動(dòng)啊
還有就是在仿真的時(shí)候結(jié)果不是很明顯喔！
以后有問(wèn)題可以請(qǐng)教你吧！QQ＝＝312097045請(qǐng)附（FPGA）  回復(fù)  更多評(píng)論   

# re: VHDL語(yǔ)言數(shù)字鐘 2007-12-29 12:41 Tim

行，一起交流！QQ:370511754  回復(fù)  更多評(píng)論   

# re: VHDL語(yǔ)言數(shù)字鐘 2008-11-07 01:03 關(guān)系字

n你的問(wèn)提也是我現(xiàn)在的問(wèn)題啊 我也在做數(shù)字鐘 我的方法是可以讓抱時(shí)間1點(diǎn)響一下 2點(diǎn)兩下.......還有一寫附加的報(bào)時(shí)功能 可能是分頻太多 有些可以信號(hào)重疊拉無(wú)法報(bào)時(shí) 報(bào)時(shí)模塊全都沒(méi)有響我想問(wèn)怎么解決   回復(fù)  更多評(píng)論   

# re: VHDL語(yǔ)言數(shù)字鐘 2008-12-14 05:52 無(wú)名小卒

請(qǐng)教一下，那個(gè)源程序用什么打開(kāi)啊，我是VHDL初學(xué)者，我安裝了max+plus2 但是打不開(kāi)，怎么打開(kāi)呢，  回復(fù)  更多評(píng)論   

# re: VHDL語(yǔ)言數(shù)字鐘 2009-01-25 09:44 Tim

各位朋友，大家好！謝謝大家的關(guān)注。這是我以前大學(xué)時(shí)做的電子課程設(shè)計(jì)，現(xiàn)在工作了，一方面是沒(méi)有從事硬件方面的；另一方面時(shí)間太忙。對(duì)不起呀！
關(guān)于打不開(kāi)的問(wèn)題，可能還是具體硬件不對(duì)應(yīng)，我找到了以前的文檔，這里附帶提供，有需要的一起參考吧@無(wú)名小卒
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# re: VHDL語(yǔ)言數(shù)字鐘 2009-04-22 08:57 acetuo

老大，你的秒表運(yùn)行不起來(lái)。在秒表狀態(tài)下，00 000，后面一個(gè)0一直閃，為8，可數(shù)字不進(jìn)行加喲，進(jìn)位，這是為啥呀。
cfungt@gmail.com
謝謝老大！??！  回復(fù)  更多評(píng)論   

# re: VHDL語(yǔ)言數(shù)字鐘 2009-05-16 16:52 baby

我也在做數(shù)字鐘的設(shè)計(jì)，波形老出不來(lái)，你能幫我看看程序有什么問(wèn)題嗎、。謝謝咯~~是用Quartus II做的。  回復(fù)  更多評(píng)論   

# re: VHDL語(yǔ)言數(shù)字鐘 2009-05-16 17:00 baby

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk:in std_logic;
clr:in std_logic;
en:in std_logic;
mode:in std_logic;
inc:in std_logic;

seg7:out std_logic_vector(6 downto 0);
scan:out std_logic_vector(5 downto 0);
sec,min:out integer range 0 to 59;
hour:out integer range 0 to 23);
end;
architecture one of clock is
signal state:std_logic_vector(1 downto 0);
signal qhh,qhl,qmh,qml,qsh,qsl:std_logic_vector(3 downto 0);
signal data:std_logic_vector(3 downto 0);
signal cnt:integer range 0 to 5;
signal clk1khz,clk1hz,clk2hz:std_logic;
signal blink:std_logic_vector(2 downto 0);
signal sec1,min1:integer range 0 to 59;
signal hour1:integer range 0 to 23;
signal inc_reg:std_logic;
begin
process(clk)
variable count:integer range 0 to 9999;
begin
if clk 'event and clk='1' then
if count=9999 then clk1khz<=not clk1khz;count:=0;
else count:=count+1;
end if;
end if;
end process;
process(clk1khz)
variable count:integer range 0 to 499;
begin
if clk1khz 'event and clk1khz='1' then
if count=499 then clk1hz<=not clk1hz;count:=0;
else count:=count+1;
end if;
end if;
end process;
process(clk1khz)
variable count:integer range 0 to 249;
begin
if clk1khz 'event and clk1khz='1' then
if count=249 then clk2hz<=not clk2hz;count:=0;
else count:=count+1;
end if;
end if;
end process;
process(mode,clr)
begin
if clr='1' then
state<="00";
elsif mode 'event and mode='1' then
state<=state+1;
end if;
end process;
process(clk1hz,state,en,clr)
begin
if clr='1' then
hour1<=0;
min1<=0;
sec1<=0;
elsif clk1hz 'event and clk1hz='1' then
case state is
when "00"=>if sec1=59 then sec1<=0;
if min1=59 then min1<=0;
if hour1=23 then hour1<=0;
else hour1<=hour1+1;
end if;
else min1<=min1+1;
end if;
else sec1<=sec1+1;
end if;
when "01"=>if inc='1' then
if inc_reg='0' then inc_reg<='1';
if hour1=23 then
hour1<=0;
else hour1<=hour1+1;
end if;
end if;
else inc_reg<='0';
end if;
when "10"=>if inc='1' then
if inc_reg='0' then inc_reg<='1';
if min1=59 then
min1<=0;
else min1<=min1+1;
end if;
end if;
else inc_reg<='0';
end if;
when "11"=>if inc='1' then
if inc_reg='0' then inc_reg<='1';
if sec1=59 then
sec1<=0;
else sec1<=sec1+1;
end if;
end if;
else inc_reg<='0';
end if;
end case;
end if;
end process;
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# re: VHDL語(yǔ)言數(shù)字鐘 2009-05-16 17:01 baby

process(state,clk2hz)
begin
case state is
when"00"=>blink<="000";
when"01"=>blink<=(2=>clk2hz,others=>'0');
when"10"=>blink<=(1=>clk2hz,others=>'0');
when"11"=>blink<=(0=>clk2hz,others=>'0');
end case;
end process;
process(sec1)
begin
case sec1 is
when 0|10|20|30|40|50=>qsl<="0000";
when 1|11|21|31|41|51=>qsl<="0001";
when 2|12|22|32|42|52=>qsl<="0010";
when 3|13|23|33|43|53=>qsl<="0011";
when 4|14|24|34|44|54=>qsl<="0100";
when 5|15|25|35|45|55=>qsl<="0101";
when 6|16|26|36|46|56=>qsl<="0110";
when 7|17|27|37|47|57=>qsl<="0111";
when 8|18|28|38|48|58=>qsl<="1000";
when 9|19|29|39|49|59=>qsl<="1001";
when others=>null;
end case;
case sec1 is
when 0|1|2|3|4|5|6|7|8|9=>qsh<="0000";
when 10|11|12|13|14|15|16|17|18|19=>qsh<="0001";
when 20|21|22|23|24|25|26|27|28|29=>qsh<="0010";
when 30|31|32|33|34|35|36|37|38|39=>qsh<="0011";
when 40|41|42|43|44|45|46|47|48|49=>qsh<="0100";
when 50|51|52|53|54|55|56|57|58|59=>qsh<="1001";
when others=>null;
end case;
end process;
process(min1)
begin
case min1 is
when 0|10|20|30|40|50=>qml<="0000";
when 1|11|21|31|41|51=>qml<="0001";
when 2|12|22|32|42|52=>qml<="0010";
when 3|13|23|33|43|53=>qml<="0011";
when 4|14|24|34|44|54=>qml<="0100";
when 5|15|25|35|45|55=>qml<="0101";
when 6|16|26|36|46|56=>qml<="0110";
when 7|17|27|37|47|57=>qml<="0111";
when 8|18|28|38|48|58=>qml<="1000";
when 9|19|29|39|49|59=>qml<="1001";
when others=>null;
end case;
case min1 is
when 0|1|2|3|4|5|6|7|8|9=>qmh<="0000";
when 10|11|12|13|14|15|16|17|18|19=>qmh<="0001";
when 20|21|22|23|24|25|26|27|28|29=>qmh<="0010";
when 30|31|32|33|34|35|36|37|38|39=>qmh<="0011";
when 40|41|42|43|44|45|46|47|48|49=>qmh<="0100";
when 50|51|52|53|54|55|56|57|58|59=>qmh<="0101";
when others=>null;
end case;
end process;
process(hour1)
begin
case hour1 is
when 0|10|20=>qhl<="0000";
when 1|11|21=>qhl<="0001";
when 2|12|22=>qhl<="0010";
when 3|13|23=>qhl<="0011";
when 4|14=>qhl<="0100";
when 5|15=>qhl<="0101";
when 6|16=>qhl<="0110";
when 7|17=>qhl<="0111";
when 8|18=>qhl<="1000";
when 9|19=>qhl<="1001";
when others=>null;
end case;
case hour1 is
when 0|1|2|3|4|5|6|7|8|9=>qhh<="0000";
when 10|11|12|13|14|15|16|17|18|19=>qhh<="0001";
when 20|21|22|23=>qhh<="0010";
when others=>null;
end case;
end process;
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# re: VHDL語(yǔ)言數(shù)字鐘 2009-05-16 17:01 baby

process(clk1khz)
begin
if clk1khz 'event and clk1khz='1' then
if cnt=5 then cnt<=0;
else cnt<=cnt+1;
end if;
end if;
end process;
process(cnt,qhh,qhl,qmh,qml,qsh,qsl,blink)
begin
case cnt is
when 0=>data<=qsl or (blink(0)&blink(0)&blink(0)&blink(0));scan<="000001";
when 1=>data<=qsh or (blink(0)&blink(0)&blink(0)&blink(0));scan<="000010";
when 2=>data<=qml or (blink(1)&blink(1)&blink(1)&blink(1));scan<="000100";
when 3=>data<=qmh or (blink(1)&blink(1)&blink(1)&blink(1));scan<="001000";
when 4=>data<=qhl or (blink(2)&blink(2)&blink(2)&blink(2));scan<="010000";
when 5=>data<=qhh or (blink(2)&blink(2)&blink(2)&blink(2));scan<="100000";
when others=>null;
end case;
end process;
process(data)
begin
case data is
when"0000"=>seg7<="1111110";
when"0001"=>seg7<="0110000";
when"0010"=>seg7<="1101101";
when"0011"=>seg7<="1111001";
when"0100"=>seg7<="0110011";
when"0101"=>seg7<="1011011";
when"0110"=>seg7<="1011111";
when"0111"=>seg7<="1110000";
when"1000"=>seg7<="1111111";
when"1001"=>seg7<="1111011";
when others=>seg7<="0000000";
end case;
end process;
sec<=sec1;
min<=min1;
hour<=hour1;
end;

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# re: VHDL語(yǔ)言數(shù)字鐘[未登錄](méi) 2013-06-19 14:23 守護(hù)

數(shù)字鐘控制器：具有時(shí)、分、秒計(jì)數(shù)顯示，以24小時(shí)循環(huán)計(jì)時(shí)；
LED動(dòng)態(tài)顯示時(shí)、分、秒；
具有清零、調(diào)節(jié)小時(shí)、分鐘、整點(diǎn)報(bào)時(shí)功能；
每小時(shí)整點(diǎn)亮一盞LED，亮30秒熄滅；
每天結(jié)束零點(diǎn)蜂鳴燈報(bào)警20秒熄滅。  回復(fù)  更多評(píng)論