2.5 CONTROL REGISTERS控制寄存器
Control
registers (CR0, CR1, CR2, CR3, and CR4; see Figure 2-6) determine operating
mode of
the processor and the characteristics of the currently executing task.
These
registers are 32 bits in all 32-bit modes and compatibility mode.
In
64-bit mode, control registers are expanded to 64 bits. The MOV CRn
instructions
are used
to manipulate the register bits. Operand-size prefixes for these instructions
are
ignored. The following is also true:
控制寄存器（CR0,CR1,CR2,CR3,CR4,看圖2-6）決定處理器的運行模式，以及當前執(zhí)行程序的一些特性。在所有32位模式以及其兼容模式下，這些寄存器都是32位的。
在64位模式下，控制寄存器擴展至64位。指令MOV CRn用于操作寄存器的位。該操作指令的前綴操作數(shù)的大小被忽略。
下面描述的內(nèi)容位真：
• Bits 63:32 of CR0 and CR4 are reserved and must be written with zeros.
Writinga nonzero value to any of the upper 32 bits results in a general-protectionexception,
#GP(0).
CR0,CR4寄存器的位32至位63保留，必須設為0.向這些為設值會誘發(fā)一個保護中斷#GP(0).
• All 64 bits of CR2 are writable by software.
CR2的64個位對于軟件都是可寫的。
• Bits 51:40 of CR3 are reserved and must be 0
CR3的位40至位52保留，必須清零。
• The MOV CRn instructions do not check that addresses written to CR2 and
CR3are within the linear-address or physical-address limitations of the
implementation.
指令MOV CRn不對將要寫入CR2和CR3的地址做合法性的檢查，即檢查是否在合法的線性地址空間或者合法的物理地址空間。
• Register CR8 is available in 64-bit mode only.
CR8只有在64模式才可用
The
control registers are summarized below, and each architecturally defined
controlfield in these control registers are described individually. In Figure
2-6, the width of
the
register in 64-bit mode is indicated in parenthesis (except for CR0).
控制寄存器如下綜述。每個架構(gòu)都在控制寄存器里定義了控制塊。稍后會對這些控制寄存器進行獨立的描述。圖26表明這些寄存器的大小是64位（除了CR0）.
• CR0 — Contains
system control flags that control operating mode and states of the processor.
包含系統(tǒng)控制標識，用以控制處理器的運行模式和狀態(tài)
• CR1 — Reserved.保留
• CR2 — Contains the
page-fault linear address (the linear address that caused apage fault).
包含頁面錯誤的線性地址（誘發(fā)頁面錯誤的線性地址）
• CR3 — Contains the
physical address of the base of the page directory and two flags (PCD and PWT).
This register is also known as the page-directory base register (PDBR). Only
the most-significant bits (less the lower 12 bits) of the base
address
are specified; the lower 12 bits of the address are assumed to be 0. The page
directory must thus be aligned to a page (4-KByte) boundary. The PCD and PWT
flags control caching of the page directory in the processor’s internal data
caches
(they do not control TLB caching of page-directory information).
CR3包含頁目錄的物理基地址和兩個標識（PCD 和PWT）.這個處理器也通常作為頁目錄基地址寄存器(PDBR).只有基地址中最重要的位（低12位）才會被指明；地址的低12位通常假設其值為0.頁表必須與頁的分界線（4KB）對齊。PCD 和PWT標識控制處理器內(nèi)部數(shù)據(jù)緩沖中的頁表緩沖（這兩個標識不控制頁表信息中的TLB緩沖）
When
using the physical address extension, the CR3 register contains the base address
of the page-directory-pointer table In IA-32e mode, the CR3 register contains
the base address of the PML4 table.
當使用物理地址的擴展特性時，CR3寄存器包含的是頁目錄指針表的基地址。在IA32E模式下，CR3寄存器包含了PML4表的基地址。
• CR4 — Contains a
group of flags that enable several architectural extensions,and indicate
operating system or executive support for specific processor capabilities.
The
control registers can be read and loaded (or modified) using the
moveto-or-from-control-registers forms of the MOV instruction. In protected
mode,the MOV instructions allow the control registers to be read or loaded (at
privilege level 0 only). This restriction means that application programs or
operatingsystem procedures (running at privilege levels 1, 2, or 3) are
prevented from reading or loading the control registers.
CR4寄存器包含一組標識，這些標識用于激活架構(gòu)的一些擴展特性，并且標明操作系統(tǒng)或服務程序為處理器的一些特殊的特性做的一些支持。
通過MOV指令，CR4寄存器可以被導入或讀取或修改。在保護模式下，MOV指令可以對CR4寄存器進行導入或讀取的操作（只有在等級0的情況下才允許）。這條約束意味著，操作系統(tǒng)或執(zhí)行程序在登記1，2，3的情況下都不被允許對CR4寄存器驚醒導入或讀取的操作。
• CR8 — Provides read
and write access to the Task Priority Register (TPR). It specifies the priority
threshold value that operating systems use to control the priority class of
external interrupts allowed to interrupt the processor. This register is
available only in 64-bit mode. However, interrupt filtering continues to apply
in compatibility mode.
CR8寄存器提供關(guān)于讀和寫任務優(yōu)先權(quán)寄存器的權(quán)限信息。被允許產(chǎn)生中斷電外部中斷都有優(yōu)先權(quán)等級；優(yōu)先權(quán)的等級是有操作系統(tǒng)去控制；而CR8提供了處理器用以控制優(yōu)先權(quán)的優(yōu)先權(quán)臨界值。CR8寄存器只在64位模式才可用。但是，兼容模式仍然提供了中斷屏蔽的功能。
When loading a
control register, reserved bits should always be set to the values previously
read. The flags in control registers are:
導入控制寄存器的值是，保留的位必須一直保留上一次讀到的值。控制寄存器里的標識如下：
PG Paging (bit 31
of CR0) — Enables paging when set; disables paging when clear. When paging
is disabled, all linear addresses are treated as physical addresses. The PG
flag has no effect if the PE flag (bit 0 of register CR0) is not also set;
setting the PG flag when the PE flag is clear causes a general protection exception
(#GP)。On Intel 64 processors,
enabling and disabling IA-32e mode operation also requires modifying CR0.PG.
PG 分頁（CR0的位31） 該標識設值時，激活分頁功能；清零則禁用分頁功能。禁用分頁時，所有的線性地址都被當作物理地址看待。如果PE標識（CR0的位0）未設值，則PG標識無任何作用。在PE標識清零的情況下，對PG標識進行設值會引發(fā)一個保護中斷（#GP）。對于intel64位處理器來說，激活和禁用IA32E模式的操作同樣需要修改CR0寄存器的PG標識。
CD Cache Disable
(bit 30 of CR0) — When the CD and NW flags are clear,caching of memory
locations for the whole of physical memory in the processor’s internal (and
external) caches is enabled. When the CD flag is set, caching is restricted as
described in Table 10-5. To prevent the processor
from accessing and
updating its caches, the CD flag must be set and the caches must be invalidated
so that no cache hits can occur.
CD 緩存禁用（CR0的位30）：當CD標識和NW標識同時清零時，內(nèi)存緩存中的處理器內(nèi)部和外部緩存被激活。當CD標識設值時，對緩存的約束有表10-5所綜述。位防止處理器訪問和更新它自己的緩存，CD標識必須設值，并且緩存必須置成無效，防止緩存請求的發(fā)生。
NW Not
Write-through (bit 29 of CR0) — When the NW and CD flags are clear,
write-back (for Pentium 4, Intel Xeon, P6 family, and Pentium processors) or
write-through (for Intel486 processors) is enabled for writes that hit the
cache and invalidation cycles are enabled. See Table 10-5 for detailed information
about the affect of the NW flag on caching for other settings of the CD and NW flags.???
AM Alignment Mask
(bit 18 of CR0) — Enables automatic alignment checking when set; disables
alignment checking when clear. Alignment checking is performed only when the AM
flag is set, the AC flag in the EFLAGS register is set, CPL is 3, and the
processor is operating in either protected or virtual-
8086 mode.
AM 數(shù)據(jù)對齊屏蔽（CR0的位18）：當該標識設值時，激活數(shù)據(jù)的自動對齊；清零時則禁用數(shù)據(jù)對齊檢查。只有在處理器在保護模式或者虛擬8086模式下運行，并且處理器權(quán)限（CPL）等級3，EFLAGS寄存器里的AC標識設值，以及AM標識設值，數(shù)據(jù)對齊檢查才會執(zhí)行。
WP Write Protect
(bit 16 of CR0) — Inhibits supervisor-level procedures from writing into
user-level read-only pages when set; allows supervisor-level procedures to
write into user-level read-only pages when clear (regardless of the U/S bit
setting; see Section 3.7.6). This flag facilitates implementation of the
copy-on-write method of creating a new process (forking) used by operating
systems such as
UNIX.
WP 寫保護（CR0的位16）：當該位設值時，阻止超級用戶的程序?qū)σ话阌脩艏墑e的只讀頁面進行寫操作；清零則允許。這個標識降低了操作系統(tǒng)創(chuàng)建新進程的copy-on-write方法的實現(xiàn)難度，比如UNIX的fork方法。
NE Numeric Error
(bit 5 of CR0) — Enables the native (internal) mechanism for reporting x87
FPU errors when set; enables the PC-style x87 FPU error reporting mechanism
when clear. When the NE flag is clear and the IGNNE#
input is asserted,
x87 FPU errors are ignored. When the NE flag is clear andthe IGNNE# input is
deasserted, an unmasked x87 FPU error causes the processor to assert the FERR#
pin to generate an external interrupt and to stop instruction execution
immediately before executing the next waiting
floating-point
instruction or WAIT/FWAIT instruction.
The FERR# pin is
intended to drive an input to an external interrupt controller (the FERR# pin
emulates the ERROR# pin of the Intel 287 and Intel 387 DX math coprocessors).
The NE flag, IGNNE# pin, and FERR# pin are used with external logic to
implement PC-style error reporting.
NE 數(shù)值錯誤（CR0的位5）：設值是激活舉報X87 FPU錯誤的內(nèi)部策略；清零時激活PC-Style X87 FPU錯誤的舉報方法。
ET Extension Type
(bit 4 of CR0) — Reserved in the Pentium 4, Intel Xeon, P6
family, and Pentium
processors. In the Pentium 4, Intel Xeon, and P6 family
processors, this
flag is hardcoded to 1. In the Intel386 and Intel486 processors,
this flag indicates
support of Intel 387 DX math coprocessor instructions
when set.
TS Task Switched (bit
3 of CR0) — Allows the saving of the x87
FPU/MMX/SSE/SSE2/
SSE3 context on a task switch to be delayed until an
x87
FPU/MMX/SSE/SSE2/SSE3 instruction is actually executed by the new
task. The processor
sets this flag on every task switch and tests it when
executing x87
FPU/MMX/SSE/SSE2/SSE3 instructions.