2.2 MODES OF OPERATION 操作的模式
The
IA-32 supports three operating modes and one quasi-operating mode:
IA32支持下面的三種操作模式和一種類似的模式
• Protected mode — This is the native operating mode of the processor. It
provides
a rich set of architectural features, flexibility, high performance and
backward
compatibility to existing software base.
保護模式：處理器本身擁有的模式。該模式提供了一個關于架構特性，系統彈性，高速運行以及向后兼容現有軟件的豐富集合。
• Real-address mode — This operating mode provides the programming
environment
of the Intel 8086 processor, with a few extensions (such as the
ability
to switch to protected or system management mode).
實地址模式：這種操作模式提供了intel8086處理器的編程環境，包括一些擴展的特性（比如在保護模式和系統管理模式之間的相互切換）
• System management mode (SMM) — SMM is a standard architectural feature
in all
IA-32 processors, beginning with the Intel386 SL processor. This mode
provides
an operating system or executive with a transparent mechanism for
implementing
power management and OEM differentiation features. SMM is
entered
through activation of an external system interrupt pin (SMI#), which
generates
a system management interrupt (SMI). In SMM, the processor
switches
to a separate address space while saving the context of the currently
running
program or task. SMM-specific code may then be executed transparently.
Upon
returning from SMM, the processor is placed back into its state prior to the
SMI.
系統管理模式（SMM）：SMM是一種自itel386 SL處理器開始，，所有IA32處理都擁有的標準架構模式。這種模式為操作系統或者程序提供了一種在電源管理，不同設備廠生的不同特性的管理等的透明的架構。SMM模式通過外部中斷(SMI#)來激活，激活的同時會產生一個系統管理中斷（SMI）。在SMM模式下，處理器在切換至獨立的地址空間的時候，會將直接保存當前程序或者當前任務的上下文。當SMM模式返回是，SMM的特定的代碼會被透明的執行。？？后面這句不懂。
• Virtual-8086 mode — In protected mode, the processor supports a quasioperating
mode
known as virtual-8086 mode. This mode allows the processor
execute
8086 software in a protected, multitasking environment.
Intel 64
architecture supports all operating modes of IA-32 architecture and IA-32e
modes:
虛擬8086模式：在保護模式下，處理器支持一種與保護模式十分類似的模式，這種模式叫虛擬8086模式。
這種模式允許處理去在一個受保護的，多任務的環境中運行8086的程序。Intel64位架構支持所有關于IA32和IA32e的模式。
• IA-32e mode — In
IA-32e mode, the processor supports two sub-modes:
compatibility
mode and 64-bit mode. 64-bit mode provides 64-bit linear
addressing
and support for physical address space larger than 64 GBytes.
Compatibility
mode allows most legacy protected-mode applications to run
unchanged.
Figure
2-3 shows how the processor moves between operating modes.
IE32E模式：在IE32E模式下，處理器支持兩種子模式：兼容模式和64位模式。64位模式提供64位的線性地址，這使得這種模式可以用于超過64GB的物理地址空間。而兼容模式則允許絕大數在保護模式下合法的程序不經修改即可在該模式上運行。圖2-3說明了處理器如何在操作模式間切換。
The
processor is placed in real-address mode following power-up or a reset. The PE
flag in
control register CR0 then controls whether the processor is operating in
realaddress
or
protected mode. See also: Section 9.9, “Mode Switching.”
當電源接通或者重啟時，處理器是在實地址模式下運行的。CR0控制寄存器里的PE標識控制處理器是在實地址模式下運行，還是在保護模式下運行。查看章節9.9.
The VM
flag in the EFLAGS register determines whether the processor is operating in
protected
mode or virtual-8086 mode. Transitions between protected mode and
virtual-8086
mode are generally carried out as part of a task switch or a return from
an
interrupt or exception handler. See also: Section 15.2.5, “Entering
Virtual-8086
Mode.”
EFLAGS寄存器里的VM標識決定處理器是運行在保護模式下，還是運行在虛擬8086模式下。通常，在一個中斷或者異常捕捉器返回，或者任務切換時，兩種模式的切換就會完成。看章節15.2.5.
The LMA
bit (IA32_EFER.LMA.LMA[bit 10]) determines whether the processor is
operating
in IA-32e mode. When running in IA-32e mode, 64-bit or compatibility
sub-mode
operation is determined by CS.L bit of the code segment. The processor
enters
into IA-32e mode from protected mode by enabling paging and setting the
LME bit
(IA32_EFER.LME[bit 8]). See also: Chapter 9, “Processor Management and
Initialization.”
（IA32_EFER_LMA_LMA的第十個字節）LMA位決定處理器是否運行在IA32E模式下。代碼段的CS.L位決定處理器是運行在IA32E模式下，還是運行在64位模式下，還是運行在兼容模式下。當設置LME位（IA32_EFER_LME的第8個自己）和啟用分頁時，處理器會自動從保護模式進入到IA32E模式。
看章節9.
The
processor switches to SMM whenever it receives an SMI while the processor is in
real-address,
protected, virtual-8086, or IA-32e modes. Upon execution of the RSM
instruction,
the processor always returns to the mode it was in when the SMI
occurred.
當處理器運行在實地址模式，或是保護模式，或是虛擬8086模式，或是IA32E模式下的時候，一旦處理器收到一個系統管理中斷，處理器就會切換至系統管理模式。當RSM指令返回時，處理器總是切換回它在系統管理模式運行之前的模式。
2.3 SYSTEM FLAGS AND FIELDS IN THE EFLAGS
REGISTER(EFLAGS寄存器的系統標識和標識塊)
The
system flags and IOPL field of the EFLAGS register control I/O, maskable
hardware
interrupts,
debugging, task switching, and the virtual-8086 mode (see
Figure
2-4). Only privileged code (typically operating system or executive code)
should
be allowed to modify these bits.
The
system flags and IOPL are:
EFLAGS寄存器里的系統標識符和IO權限等級塊控制 I/O，硬件中斷的屏蔽，調試，任務切換和虛擬8086模式（看圖2-4），只有權限操作代碼（以操作系統代碼或者程序代碼為代表）才被允許修改這些位的值。
下面是系統標識和IO權限控制塊的內容：
TF Trap
(bit 8) — Set to enable single-step mode for debugging; clear to
disable
single-step mode. In single-step mode, the processor generates a
debug
exception after each instruction. This allows the execution state of a
program
to be inspected after each instruction. If an application program
sets the
TF flag using a POPF, POPFD, or IRET instruction, a debug exception
is
generated after the instruction that follows the POPF, POPFD, or IRET.
TF陷入（第8位）：設值的時候激活調試的單步執行模式；清零則禁止單步執行模式。在單步執行模式下，處理器會在每條指令執行后產生一個調試異常中斷，中斷后允許查看每條指令執行后程序的狀態。當程序用OPPF,OPOFD,或IRET指令來設置TF標識的時候，POPF,POPFD,IRET后的第一條指令會誘發一個調試異常中斷。
IF Interrupt
enable (bit 9) — Controls the response of the processor to
maskable
hardware interrupt requests (see also: Section 5.3.2, “Maskable
Hardware
Interrupts”). The flag is set to respond to maskable hardware
interrupts;
cleared to inhibit maskable hardware interrupts. The IF flag does
not
affect the generation of exceptions or nonmaskable interrupts (NMI
interrupts).
The CPL, IOPL, and the state of the VME flag in control register
CR4
determine whether the IF flag can be modified by the CLI, STI, POPF,
POPFD,
and IRET.
IF 中斷激活（第9位）：控制處理器對硬件中斷屏蔽要求的相應（查看章節5.3.2）。該標識為設值這激活處理器對硬件中斷屏蔽的響應，清零這阻止硬件中斷屏蔽。IF標識不影響非硬件中斷（NMI）和異常。CR4寄存器里的VME標識，和CPL,IPOL一起決定指令CLI,STI,POPF,POPFD,IRET是否能修改IF標識的值。
IOPL I/O
privilege level field (bits 12 and 13) — Indicates the I/O privilege
level
(IOPL) of the currently running program or task. The CPL of the
currently
running program or task must be less than or equal to the IOPL to
access
the I/O address space. This field can only be modified by the POPF
and IRET
instructions when operating at a CPL of 0.
The IOPL
is also one of the mechanisms that controls the modification of the
IF flag
and the handling of interrupts in virtual-8086 mode when virtual
mode
extensions are in effect (when CR4.VME = 1). See also: Chapter 13,
“Input/Output,” in the Intel® 64 and IA-32
Architectures Software Developer’s
Manual, Volume 1.
I
I/O權限等級快（位12和位13）：這兩個位表明了當前運行的程序或任務的I/O權限等級。當前程序或任務的處理器權限等級（CPL）一定要比前程序或任務要訪問的I/O地址空間的I/O權限等級要低。只有指令OPPF和IRET在處理器權限等級0的狀態下才能修改這塊的數值。查看章節13.
NT Nested
task (bit 14) — Controls the chaining of interrupted and called
tasks.
The processor sets this flag on calls to a task initiated with a CALL
instruction,
an interrupt, or an exception. It examines and modifies this flag
on
returns from a task initiated with the IRET instruction. The flag can be
explicitly
set or cleared with the POPF/POPFD instructions; however,
changing
to the state of this flag can generate unexpected exceptions in
application
programs.
See
also: Section 6.4, “Task Linking.”
NT內嵌任務（位14）：控制被中斷任務和被調用任務的鏈。當通過指令CALL，中斷，或是異常調用任務時，處理器就會設置該標識的值。當一個任務通過IRET指令返回時，處理器會檢查和修改該標識的值。雖然可以通過POPF/IRET指令來設置或清零該標識的值，但改變這個標識的狀態可能會引發一些程序的意外的異常。
RF Resume
(bit 16) — Controls the processor’s response to instruction-breakpoint
conditions.
When set, this flag temporarily disables debug exceptions
(#DB)
from being generated for instruction breakpoints (although other
exception
conditions can cause an exception to be generated). When clear,
instruction
breakpoints will generate debug exceptions.
The primary
function of the RF flag is to allow the restarting of an instruction
following
a debug exception that was caused by an instruction breakpoint
condition.
Here, debug software must set this flag in the EFLAGS image on
the
stack just prior to returning to the interrupted program with IRETD (to
prevent
the instruction breakpoint from causing another debug exception).
The
processor then automatically clears this flag after the instruction
returned
to has been successfully executed, enabling instruction breakpoint
faults
again.
See
also: Section 18.3.1.1, “Instruction-Breakpoint Exception Condition.”
RF(重設)（位16）：該標識控制處理器對指令的斷點情況的響應。該標識設值就會暫時禁止指令斷點產生調試異常（雖然其他的異常會誘發產生一個異常）；清零的時候，激活指令斷點產生調試異常。指令斷點狀態產生的異常，可以在調試異常后的第一條指令，通過RF標識的函數重新誘發。調試中的程序必須在程序因為IRETD而中斷返回之前，設置棧里的EFLAGS寄存器鏡像的RF標識（防止指令斷點引發另外一個調試異常）。處理器會在返回指令成功執行后，自動清零該標識，并且重新激活指令錯誤。
VM Virtual-8086
mode (bit 17) — Set to enable virtual-8086 mode; clear to
return
to protected mode.
See
also: Section 15.2.1, “Enabling Virtual-8086 Mode.”
VM 虛擬8086模式（位17）：設值則激活虛擬8086模式，清零則返回保護模式。查看章節15.2.1.
AC Alignment
check (bit 18) — Set this flag and the AM flag in control register
CR0 to
enable alignment checking of memory references; clear the AC flag
and/or
the AM flag to disable alignment checking. An alignment-check
exception
is generated when reference is made to an unaligned operand,
such as
a word at an odd byte address or a doubleword at an address which
is not
an integral multiple of four. Alignment-check exceptions are generated
only in
user mode (privilege level 3). Memory references that default to privilege
level 0,
such as segment descriptor loads, do not generate this exception
even
when caused by instructions executed in user-mode.
The
alignment-check exception can be used to check alignment of data. This
is
useful when exchanging data with processors which require all data to be
aligned.
The alignment-check exception can also be used by interpreters to
flag
some pointers as special by misaligning the pointer. This eliminates
overhead
of checking each pointer and only handles the special pointer when
used.
AC 數據對齊檢查（位18） 通過設置CR0控制寄存器中的該標識和AM標識，可以激活內存引用的數據對齊檢查，清零該標識（AM清零不是必須的）則禁止數據對齊檢查。當內存引用的數據是由無法直接構成對齊的操作數組成的時候，一個數據對齊異常便會產生，比如零碎地址上的一個字，或者不是四的倍數的地址上的一個雙字。數據對齊異常只會在用戶模式（等級3）下產生。因為用戶模式下的指令執行而導致的，類似段描述符導入等在等級0上的內存數據引用，是不會誘發數據對齊異常的。
數據對齊異常可以用于檢查數據的對齊。因為處理器要求所有數據必須對齊，因此，在和處理器交換數據時，進行數據對齊的檢查，是非常有用的。在解釋程序標明一些特殊的指針，比如調整指針的位置時，通過使用數據對齊異常，可以不必對每個指針進行過度的檢查，只需處理正在使用的特殊指針。？？
VIF Virtual
Interrupt (bit 19) — Contains a virtual image of the IF flag. This
flag is
used in conjunction with the VIP flag. The processor only recognizes
the VIF
flag when either the VME flag or the PVI flag in control register CR4 is
set and
the IOPL is less than 3. (The VME flag enables the virtual-8086 mode
extensions;
the PVI flag enables the protected-mode virtual interrupts.)
See
also: Section 15.3.3.5, “Method 6: Software Interrupt Handling,” and
Section
15.4, “Protected-Mode Virtual Interrupts.”
VIF 虛擬終端（位19） ：包含了IF標識的一個虛擬鏡像。VIF標識和VME標識一起使用。只有當IOPL的權限等級小于3，并且CR4控制寄存器里的整個VME標識或者整個PVI標識被設值，處理器才會識別VIF標識。（VME標識激活虛擬8086模式的擴展特性；PVI標識激活保護模式的虛擬終端）。度章節15.3.3.5.
VIP Virtual
interrupt pending (bit 20) — Set by software to indicate that an
interrupt
is pending; cleared to indicate that no interrupt is pending. This flag
is used
in conjunction with the VIF flag. The processor reads this flag but
never
modifies it. The processor only recognizes the VIP flag when either the
VME flag
or the PVI flag in control register CR4 is set and the IOPL is less than
3. The
VME flag enables the virtual-8086 mode extensions; the PVI flag
enables
the protected-mode virtual interrupts.
VIP 虛擬中斷等待（位20）： 該標識表明一個中斷被等待，且該位是通過程序來設值得。清零表明無中斷被等待。該標識和VIF標識一起使用。處理會讀取該標識但從來不修改標識的值。只有IOPL等級小于3，并且CR4控制寄存器里的VME標識或者PVI標識被設值，處理器才會識別該標識。VME標識激活虛擬8086的擴展特性，PVI標識激活保護模式的虛擬終端。
ID Identification
(bit 21). — The ability of a program or procedure to set or
clear
this flag indicates support for the CPUID instruction.
ID 身份驗證(位21)： 程序可以對該標識設值或者清零。該標識用以表明對CPUID指令的支持。
2.3.1 System Flags and Fields in IA-32e Mode（IA32E模式的系統標識和系統標識塊）
In
64-bit mode, the RFLAGS register expands to 64 bits with the upper 32 bits
reserved.
System flags in RFLAGS (64-bit mode) or EFLAGS (compatibility mode)
are
shown in Figure 2-4.
在64模式下，EFLAGS寄存器擴展至64位，而高32位是保留的。EFLAGS寄存器里的系統標識如圖2.4所示。
In
IA-32e mode, the processor does not allow the VM bit to be set because virtual-
8086
mode is not supported (attempts to set the bit are ignored). Also, the
processor
will not
set the NT bit. The processor does, however, allow software to set the NT bit
(note
that an IRET causes a general protection fault in IA-32e mode if the NT bit is
set).
虛擬8086模式不支持VM標識，故在IA32E模式下，處理器不允許設置VM標識（即使設置也會被忽略）。
同樣，處理器也不設置NT位.但是允許軟件設置NT位（如果NT被設值，IRET會誘發一個保護錯誤）
In
IA-32e mode, the SYSCALL/SYSRET instructions have a programmable method of
specifying
which bits are cleared in RFLAGS/EFLAGS. These instructions save/restore
EFLAGS/RFLAGS.
在IA32E模式下，指令SYSCALL/SYSRET都有一個可編程的方法來識別RFLAGS/EFLAGS寄存器里的那些位被清零了。這些指令可以保存/重新保存EFLAGS/RFLAGS的值。
2.4 MEMORY-MANAGEMENT REGISTERS內存管理寄存器
The
processor provides four memory-management registers (GDTR, LDTR, IDTR,
and TR)
that specify the locations of the data structures which control segmented
memory
management (see Figure 2-5). Special instructions are provided for loading
and
storing these registers.
處理器提供了四個內存管理寄存器（GDTR,LDTR,IDTR,和TR）,這些寄存器用于查詢控制分段內存管理的數據結構的位置。（看圖2-5）一些特別的指令用于導入和保存這些寄存器的值。
2.4.1 Global Descriptor Table Register (GDTR)全局描述符符表寄存器
The GDTR
register holds the base address (32 bits in protected mode; 64 bits in
IA-32e
mode) and the 16-bit table limit for the GDT. The base address specifies the
linear
address of byte 0 of the GDT; the table limit specifies the number of bytes in
the
table.
全局描述符表寄存器由基地址（保護模式為32位，IA32E位64位），16位表長限制組成。基地址指明GDT的第0個字節的線性地址；表長限制指明表里的字節數目。
The LGDT
and SGDT instructions load and store the GDTR register, respectively. On
power up
or reset of the processor, the base address is set to the default value of 0
and the
limit is set to 0FFFFH. A new base address must be loaded into the GDTR as
part of
the processor initialization process for protected-mode operation.
See
also: Section 3.5.1, “Segment Descriptor Tables.”
指令LGDT和SGDT用以導入和保存GDTR寄存器。當電源接通或者處理重啟時，GDT的基地值設置成默認值0，而表長限制被設置成OFFFFH。保護模式下，作為處理器初始化進程的一部分，GDTR的新地址必須被導入。
2.4.2 Local Descriptor Table Register (LDTR)局部描述符表寄存器
The LDTR
register holds the 16-bit segment selector, base address (32 bits in
protected
mode; 64 bits in IA-32e mode), segment limit, and descriptor attributes
for the
LDT. The base address specifies the linear address of byte 0 of the LDT
segment;
the segment limit specifies the number of bytes in the segment. See also:
Section
3.5.1, “Segment Descriptor Tables.”
LDTR寄存器由16段選擇器，基地址（保護模式為32位，IA32E模式為64位）,段長限制，以及LDT的描述符屬性組成。基地值知名LDT的第0字節的線性地址。段長限制知名段的字節數目；
The LLDT
and SLDT instructions load and store the segment selector part of the LDTR
register,
respectively. The segment that contains the LDT must have a segment
descriptor
in the GDT. When the LLDT instruction loads a segment selector in the
LDTR:
the base address, limit, and descriptor attributes from the LDT descriptor are
automatically
loaded in the LDTR.
指令LLDT和SLDT用于導入和保存LDTR的段選擇器部分。包含LDT的段用于一個在GDT里的段描述符。當LLDT指令導入LDTR里的段選擇器的時候，基地址，段長顯示，描述符屬性會給自動導入到LDTR里。
When a
task switch occurs, the LDTR is automatically loaded with the segment
selector
and descriptor for the LDT for the new task. The contents of the LDTR are not
automatically
saved prior to writing the new LDT information into the register.
On power
up or reset of the processor, the segment selector and base address are set
to the
default value of 0 and the limit is set to 0FFFFH.
發生任務切換時，新任務的LDT里的段選擇器，描述符自動導入LDTR里。在將新的LDT信息寫入到寄存器之前，LDTR里的內容不會自動保存。電源接通或者處理器重啟，選擇器和基地址被設置成默認值0，段長限制被設置成0FFFFH。
2.4.3 IDTR Interrupt Descriptor Table Register IDTR中斷描述符表寄存器
The IDTR
register holds the base address (32 bits in protected mode; 64 bits in
IA-32e
mode) and 16-bit table limit for the IDT. The base address specifies the linear
address
of byte 0 of the IDT; the table limit specifies the number of bytes in the
table.
The LIDT
and SIDT instructions load and store the IDTR register, respectively. On
power up
or reset of the processor, the base address is set to the default value of 0
and the
limit is set to 0FFFFH. The base address and limit in the register can then be
changed
as part of the processor initialization process.
See
also: Section 5.10, “Interrupt Descriptor Table (IDT).”
IDTR寄存器由基地址（保護模式為32位，IA32E模式為64位），16位IDT表長限制組成。基地址知名IDT的第0個字節的線性地址。表長限制指明表的字節數目。指令LIDT和SIDT分別用于導入和保存IDTR寄存器里的值。電源接通或者處理器重啟時，基地址被設置成默認值0，段長限制被設置成0FFFFH。處理器初始化進程時，作為初始化的一部分，寄存器里的基地址和段長顯示可以發生變化。
2.4.4 Task Register (TR) 任務寄存器
The task
register holds the 16-bit segment selector, base address (32 bits in
protected
mode; 64 bits in IA-32e mode), segment limit, and descriptor attributes
for the
TSS of the current task. The selector references the TSS descriptor in the GDT.
The base
address specifies the linear address of byte 0 of the TSS; the segment limit
specifies
the number of bytes in the TSS. See also: Section 6.2.4, “Task Register.”
The LTR
and STR instructions load and store the segment selector part of the task
register,
respectively. When the LTR instruction loads a segment selector in the task
register,
the base address, limit, and descriptor attributes from the TSS descriptor
are
automatically loaded into the task register. On power up or reset of the
processor,
the base
address is set to the default value of 0 and the limit is set to 0FFFFH.
When a
task switch occurs, the task register is automatically loaded with the
segment
selector and descriptor for the TSS for the new task. The contents of the
task
register are not automatically saved prior to writing the new TSS information
into the
register.
任務寄存器由16位段選擇器，基地址（保護模式為32位，IA32E模式為64位），段長限制，以及當前任務的任務狀態段的段描述符屬性組成。選擇器指向GDT里的任務狀態段的描述符。基地址指明任務狀態段的第0個字節的線性地址。
指令LTR和STR分別用于導入和保存任務寄存器里的段選擇器部分。使用LTR指令導入任務寄存器的段選擇器的時候，TSS描述符的屬性，基地址，段長顯示會被自動導入。電源接通或處理器重啟時，基地址被設置成默認值0，段長限制被設置成0FFFFH。發生任務切換時，新任務的任務狀態段的段選擇器和描述符會被自動導入到TR寄存器中。在新任務的TSS信息導入到寄存器之前，TR寄存器里面的內容不會被自動保存。