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            ARM 嵌入式學(xué)習(xí)筆記 (一)

            I. Programmer's Model
              1. ARM instruction set
                 Branch instructions
                 Data-processing instructions
                 Status register transfer instructions
                 Load and store instructions
                 Coprocessor instructions
                 Exception-generating instructions
             
              2. Processor modes
                 Processor mode     Description
                 ----------------   -------------------------------------------------------
                 User          usr     Normal program execution mode
                 FIQ           fiq     Supports a high-speed data transfer or channel process
                 IRQ           irq     Used for general-purpose interrupt handling
                 Supervisor svc     A protected mode for operating system
                 Abort        abt     Implements virtual memory and/or memory protection
                 Undefined  und     Support software emulation of hardware coprocessors
                 System       sys     Runs privileged operating system tasks
             
              3. Registers
                 (1) 31 general-purpose registers, including PC.
                 (2) 6 status registers, these registers are also 32 bits, but only 12 of
                     32 bits are allocated or need to be implemented.
                 (3) At any time, 15 general-purpose registers (R0~R14), one or two status
                     registers and the program counter are visible.
                 (4) The general-purpose registers R0~R15 can be split into three groups:
                     The unbanked registers: R0~R7
                     The banked registers: R8~R15
                     Register 15, the PC, is described in the Program counter
                 (5) Banked registers means that each of them refers to the same 32-bit
                     physical register in all processor modes; Unbanked registers means
                     the physical register referred to by each of them depends on the
                     current processor mode.

              4. Exceptions
                 (1)ARM supports seven types of exception, following table lists the types
                    of exception and the processor mode that is used to process that
                    exception:
                    -----------------------------------------------------------------------
                    Exception               Mode              Normal             High Vector
                                                                         adddress           address
                    -----------------------------------------------------------------------
                    Reset                      Supervisor      0x00000000      0xFFFF0000
                    Undefined               Undefined       0x00000004      0xFFFF0004
                    Software Interupt    Supervistor     0x00000008      0xFFFF0008
                    Prefetch Abort        Abort             0x0000000C      0xFFFF000C
                    Data Abort             Abort             0x00000010       0xFFFF0010
                    IRQ (interupt)         IRQ               0x00000018       0xFFFF0018
                    FIQ (fase interupt)  FIQ               0x0000001C       0xFFFF001C
                    -----------------------------------------------------------------------
                   
               Note: The normal vector at address 0x000014 and the high vector address
                     at 0xFFFF0014 are not normally used and are reserved for furture
                     expansion.
                 (2) An interupt handler that wishes to store its return link on the stack
                     might use instrcutions of following form at its entry point:
                    
                     SUB    R14, R14, #4
                     STMFD  SP!, {<other_registers>, R14}

                     and return using the instruction:

                     LDMFD  SP!, {<other_registers>, PC}^

                 (3) Exception priorities
                     ---------------------------------------------
                      Priority         Exception
                     ---------------------------------------------
                              1          Reset
                     ---------------------------------------------
                              2          Data Abort
                     ---------------------------------------------
                              3          FIQ
                     ---------------------------------------------
                              4          IRQ
                     ---------------------------------------------
                              5          Prefetch Abort
                     ---------------------------------------------
                              6          Undefined instruction
                                         SWI
                     ---------------------------------------------
                    
               5. Memory and memory-mapped I/O
                  (1) Address align
                      ARM address is word-aligned which means that the address is divisible
                      by 4(actually the last two bits of that address are 0)

                  (2) Endianness
                      In a little-endian memory system:
                      A byte or halfword at word-aligned address is the least significant
                      byte or halfword within the word at that address

                      In a big-endian memory system:
                      A byte or halfword at word-aligned address is the most significant
                      byte or halfword with the word at that address

                  (3) Memory-mapped I/O
                      This uses special memory addresses which supply I/O functions when
                      they loaded from or stored to.

             

            posted on 2008-01-02 18:16 Normandy 閱讀(1834) 評(píng)論(1)  編輯 收藏 引用 所屬分類: Embeded Area

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