Static timing analysis is a critical step in design of any digitalintegrated circuit. Technology and design trends have ledto significant increase in environmental and process variationswhich need to be incorporated in static timing analysis.This paper presents a new, efficient and accurate block-basedstatic timing analysis technique considering uncertainty.This new method is more efficient as its modelsarrival times as cumulative density functions (CDFs) anddelays as probability functions (PDFs). Computationallysimple expression are presented for basic static timing operations.The techniques are valid for any form of the probabilitydistribution, though the use piecewise linear modelingof CDFs is highlighted in this paper. Reconvergent fanoutsare handled using a new technique that avoids path tracing.Variable accuracy timing analysis can be performed byvarying the modeling accuracy of the piecewise linearmodel. Regular and statistical timing on different parts ofthe circuit can be incorporated into a single timing analysisrun. Accuracy and efficiency of the proposed method is demonstratedfor various ISCAS benchmark circuits.

1. ideal

2. latency

3. skew= Tmax-Tmin

4. clock uncertainty

5. jitter （y軸 振幅）

6. glitch(值變化，波形上有個(gè)毛刺，x軸)

7. launch and the capture clock paths